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• What Is Ddr2 Ram

Double Data Rate 2 Synchronous Dynamic Random-Access Memory, officially abbreviated as DDR2 SDRAM, is a double data ratesynchronous dynamic random-access memoryinterface. It superseded the original DDR SDRAM specification, and is superseded by DDR3 SDRAM (launched in 2007). DDR2 DIMMs are neither forward compatible with DDR3 nor backward compatible with DDR.

In addition to double pumping the data bus as in DDR SDRAM (transferring data on the rising and falling edges of the bus clock signal), DDR2 allows higher bus speed and requires lower power by running the internal clock at half the speed of the data bus. The two factors combine to produce a total of four data transfers per internal clock cycle.

Since the DDR2 internal clock runs at half the DDR external clock rate, DDR2 memory operating at the same external data bus clock rate as DDR results in DDR2 being able to provide the same bandwidth but with better latency. Alternatively, DDR2 memory operating at twice the external data bus clock rate as DDR may provide twice the bandwidth with the same latency. The best-rated DDR2 memory modules are at least twice as fast as the best-rated DDR memory modules.The maximum capacity on commercially available DDR2 DIMMs is 4GB, but chipset support and availability for those DIMMs is sparse and more common 2GB per DIMM are used.^{[citation needed]}

• 2Specification

Oct 11, 2008  Hello all, I just recently bought a new Sony Vaio, but purposely chose 1 GB of DDR2 800 ram so that I could upgrade it to 4 GB myself. The problem I have now is, looking through various RAM's online, I see that there are two types of pin configurations for DDR2 800/PC6400 RAM: 240 and 200.

History[edit]

DDR2 SDRAM was first produced by Samsung in 2001. In 2003, the JEDEC standards organization presented Samsung with its Technical Recognition Award for the company's efforts in developing and standardizing DDR2.^[1]

DDR2 was officially introduced in the second quarter of 2003 at two initial clock rates: 200 MHz (referred to as PC2-3200) and 266 MHz (PC2-4200). Both performed worse than the original DDR specification due to higher latency, which made total access times longer. However, the original DDR technology tops out at a clock rate around 200 MHz (400 MT/s). Higher performance DDR chips exist, but JEDEC has stated that they will not be standardized. These chips are mostly standard DDR chips that have been tested and rated to be capable of operation at higher clock rates by the manufacturer. Such chips draw significantly more power than slower-clocked chips, but usually offered little or no improvement in real-world performance. DDR2 started to become competitive against the older DDR standard by the end of 2004, as modules with lower latencies became available.^[2]

Specification[edit]

Overview[edit]

What Is Ddr2 Ram

The key difference between DDR2 and DDR SDRAM is the increase in prefetch length. In DDR SDRAM, the prefetch length was two bits for every bit in a word; whereas it is four bits in DDR2 SDRAM. During an access, four bits were read or written to or from a four-bit-deep prefetch queue. This queue received or transmitted its data over the data bus in two data bus clock cycles (each clock cycle transferred two bits of data. Increasing the prefetch length allowed DDR2 SDRAM to double the rate at which data could be transferred over the data bus without a corresponding doubling in the rate at which the DRAM array could be accessed. DDR2 SDRAM was designed with such a scheme to avoid an excessive increase in power consumption.

DDR2's bus frequency is boosted by electrical interface improvements, on-die termination, prefetch buffers and off-chip drivers. However, latency is greatly increased as a trade-off. The DDR2 prefetch buffer is four bits deep, whereas it is two bits deep for DDR. While DDR SDRAM has typical read latencies of between two and three bus cycles, DDR2 may have read latencies between three and nine cycles, although the typical range is between four and six. Thus, DDR2 memory must be operated at twice the data rate to achieve the same latency.

Another cost of the increased bandwidth is the requirement that the chips are packaged in a more expensive and difficult to assemble BGA package as compared to the TSSOP package of the previous memory generations such as DDR SDRAM and SDR SDRAM. This packaging change was necessary to maintain signal integrity at higher bus speeds.

Power savings are achieved primarily due to an improved manufacturing process through die shrinkage, resulting in a drop in operating voltage (1.8 V compared to DDR's 2.5 V). The lower memory clock frequency may also enable power reductions in applications that do not require the highest available data rates.

According to JEDEC^[3] the maximum recommended voltage is 1.9 volts and should be considered the absolute maximum when memory stability is an issue (such as in servers or other mission critical devices). In addition, JEDEC states that memory modules must withstand up to 2.3 volts before incurring permanent damage (although they may not actually function correctly at that level).

Chips and modules[edit]

For use in computers, DDR2 SDRAM is supplied in DIMMs with 240 pins and a single locating notch. Laptop DDR2 SO-DIMMs have 200 pins and often come identified by an additional S in their designation. DIMMs are identified by their peak transfer capacity (often called bandwidth).

* Some manufacturers label their DDR2 modules as PC2-4300, PC2-5400 or PC2-8600 instead of the respective names suggested by JEDEC. At least one manufacturer has reported this reflects successful testing at a higher-than-standard data rate^[7] whilst others simply round up for the name.

Note: DDR2-xxx denotes data transfer rate, and describes raw DDR chips, whereas PC2-xxxx denotes theoretical bandwidth (with the last two digits truncated), and is used to describe assembled DIMMs. Bandwidth is calculated by taking transfers per second and multiplying by eight. This is because DDR2 memory modules transfer data on a bus that is 64 data bits wide, and since a byte comprises 8 bits, this equates to 8 bytes of data per transfer.

In addition to bandwidth and capacity variants, modules can:

1. Optionally implement ECC, which is an extra data byte lane used for correcting minor errors and detecting major errors for better reliability. Modules with ECC are identified by an additional ECC in their designation. PC2-4200 ECC is a PC2-4200 module with ECC. An additional P can be added at the end of the designation, P standing for parity (ex : PC2-5300P).
2. Intel ® 6402 Advanced Memory Buffer
   Be 'registered' ('buffered'), which improves signal integrity (and hence potentially clock rates and physical slot capacity) by electrically buffering the signals at a cost of an extra clock of increased latency. Those modules are identified by an additional R in their designation, whereas non-registered (a.k.a. 'unbuffered') RAM may be identified by an additional U in the designation. PC2-4200R is a registered PC2-4200 module, PC2-4200R ECC is the same module but with additional ECC.
3. Be aware fully buffered modules, which are designated by F or FB do not have the same notch position as other classes. Fully buffered modules cannot be used with motherboards that are made for registered modules, and the different notch position physically prevents their insertion.

Note:

• Registered and un-buffered SDRAM generally cannot be mixed on the same channel.
• The highest-rated DDR2 modules in 2009 operate at 533 MHz (1066 MT/s), compared to the highest-rated DDR modules operating at 200 MHz (400 MT/s). At the same time, the CAS latency of 11.2 ns = 6 / (bus clock rate) for the best PC2-8500 modules is comparable to that of 10 ns = 4 / (bus clock rate) for the best PC-3200 modules.

Backward compatibility[edit]

DDR2 DIMMs are not backward compatible with DDR DIMMs. The notch on DDR2 DIMMs is in a different position from DDR DIMMs, and the pin density is higher than DDR DIMMs in desktops. DDR2 is a 240-pin module, DDR is a 184-pin module. Notebooks have 200-pin SO-DIMMs for DDR and DDR2; however, the notch on DDR2 modules is in a slightly different position than on DDR modules.

Higher-speed DDR2 DIMMs can be mixed with lower-speed DDR2 DIMMs, although the memory controller will operate all DIMMs at same speed as the lowest-speed DIMM present.

Relation to GDDR memory[edit]

GDDR2, a form of GDDR SDRAM, was developed by Samsung and introduced in July 2002.^[8] The first commercial product to claim using the 'DDR2' technology was the NvidiaGeForce FX 5800 graphics card. However, it is important to note that this GDDR2 memory used on graphics cards is not DDR2 per se, but rather an early midpoint between DDR and DDR2 technologies. Using 'DDR2' to refer to GDDR2 is a colloquialmisnomer. In particular, the performance-enhancing doubling of the I/O clock rate is missing. It had severe overheating issues due to the nominal DDR voltages. ATI has since designed the GDDR technology further into GDDR3, which is based on DDR2 SDRAM, though with several additions suited for graphics cards.

GDDR3 and GDDR5 is now commonly used in modern graphics cards and some tablet PCs. However, further confusion has been added to the mix with the appearance of budget and mid-range graphics cards which claim to use 'GDDR2'. These cards actually use standard DDR2 chips designed for use as main system memory although operating with higher latencies to achieve higher clockrates. These chips cannot achieve the clock rates of GDDR3 but are inexpensive and fast enough to be used as memory on mid-range cards.

See also[edit]

• CAS latency (definition of 'CAS 5-5-5-15', for example)

References[edit]

1. ^ ^ab'Samsung Demonstrates World's First DDR 3 Memory Prototype'. Phys.org. 17 February 2005. Retrieved 23 June 2019.
2. ^Ilya Gavrichenkov. 'DDR2 vs. DDR: Revenge gained'. X-bit Laboratories. Archived from the original on 2006-11-21.
3. ^JEDEC JESD 208 (section 5, tables 15 and 16)
4. ^Cycle time is the inverse of the I/O bus clock frequency; e.g., 1/(100 MHz) = 10 ns per clock cycle.
5. ^'DDR2 SDRAM SPECIFICATION'(PDF). JESD79-2E. JEDEC. April 2008: 78. Retrieved 2009-03-14.Cite journal requires |journal= (help)
6. ^'SPECIALITY DDR2-1066 SDRAM'(PDF). JEDEC. November 2007: 70. Retrieved 2009-03-14.Cite journal requires |journal= (help)
7. ^Mushkin PC2-5300 vs. Corsair PC2-5400
8. ^'Samsung Electronics Announces JEDEC-Compliant 256Mb GDDR2 for 3D Graphics'. Samsung Electronics. Samsung. 23 August 2003. Retrieved 26 June 2019.

Further reading[edit]

• JEDEC standard: DDR2 SDRAM Specification: JESD79-2F, November 2009 ** http://www.jedec.org/standards-documents/docs/jesd-79-2e
• JEDEC standard: DDR2-1066 **
• 'JEDEC Standard No. 21C: 4.20.13 240-Pin PC2-5300/PC2-6400 DDR2 SDRAM Unbuffered DIMM Design Specification' **
• JEDEC Solid State Technology Association
• Razak Mohammed Ali. 'DDR2 SDRAM interfaces for next-gen systems'(PDF). Electronic Engineering Times. Archived from the original(PDF) on 2007-09-26.

Note**: JEDEC website requires registration ($2,500 membership) for viewing or downloading of these documents: http://www.jedec.org/standards-documents

External links[edit]

A DIMM or dual in-line memory module comprises a series of dynamic random-access memoryintegrated circuits. These modules are mounted on a printed circuit board and designed for use in personal computers, workstations and servers. DIMMs began to replace SIMMs (single in-line memory modules) as the predominant type of memory module as IntelP5-based Pentium processors began to gain market share.

While the contacts on SIMMs on both sides are redundant, DIMMs have separate electrical contacts on each side of the module. Another difference is that standard SIMMs have a 32-bit data path, while standard DIMMs have a 64-bit data path. Since Intel's Pentium, many processors have a 64-bit bus width, requiring SIMMs installed in matched pairs in order to populate the data bus. The processor would then access the two SIMMs in parallel. DIMMs were introduced to eliminate this disadvantage.

Variants[edit]

Variants of DIMM slots support DDR, DDR2, DDR3 and DDR4 RAM.

Common types of DIMMs include the following:

70 to 200 pins

• 72-pin SO-DIMM (not the same as a 72-pin SIMM), used for FPM DRAM and EDO DRAM
• 100-pin DIMM, used for printer SDRAM
• 144-pin SO-DIMM, used for SDR SDRAM (less frequently for DDR2 SDRAM)
• 168-pin DIMM, used for SDR SDRAM (less frequently for FPM/EDO DRAM in workstations/servers, may be 3.3 or 5 V)
• 172-pin MicroDIMM, used for DDR SDRAM
• 184-pin DIMM, used for DDR SDRAM
• 200-pin SO-DIMM, used for DDR SDRAM and DDR2 SDRAM
• 200-pin DIMM, used for FPM/EDO DRAM in some Sun workstations and servers.

201 to 300 pins

• 204-pin SO-DIMM, used for DDR3 SDRAM
• 214-pin MicroDIMM, used for DDR2 SDRAM
• 240-pin DIMM, used for DDR2 SDRAM, DDR3 SDRAM and FB-DIMM DRAM
• 244-pin MiniDIMM, used for DDR2 SDRAM
• 260-pin SO-DIMM, used for DDR4 SDRAM
• 260-pin SO-DIMM, with different notch position than on DDR4 SO-DIMMs, used for UniDIMMs that can carry either DDR3 or DDR4 SDRAM
• 278-pin DIMM, used for HP high density SDRAM.
• 288-pin DIMM, used for DDR4 SDRAM

168-pin SDRAM[edit]

On the bottom edge of 168-pin DIMMs there are two notches, and the location of each notch determines a particular feature of the module. The first notch is the DRAM key position, which represents RFU (reserved future use), registered, and unbuffered DIMM types (left, middle and right position, respectively). The second notch is the voltage key position, which represents 5.0 V, 3.3 V, and RFU DIMM types (order is the same as above).

DDR DIMMs[edit]

DDR, DDR2, DDR3 and DDR4 all have different pin counts, and different notch positions. As of August, 2014, DDR4 SDRAM is a modern emerging type of dynamic random access memory (DRAM) with a high-bandwidth ('double data rate') interface, and has been in use since 2013. It is the higher-speed successor to DDR, DDR2 and DDR3. DDR4 SDRAM is neither forward nor backward compatible with any earlier type of random access memory (RAM) because of different signalling voltages, timings, as well as other differing factors between the technologies and their implementation.

SPD EEPROM[edit]

A DIMM's capacity and other operational parameters may be identified with serial presence detect (SPD), an additional chip which contains information about the module type and timing for the memory controller to be configured correctly. The SPD EEPROM connects to the System Management Bus and may also contain thermal sensors (TS-on-DIMM).^[1]

Error correction[edit]

ECC DIMMs are those that have extra data bits which can be used by the system memory controller to detect and correct errors. There are numerous ECC schemes, but perhaps the most common is Single Error Correct, Double Error Detect (SECDED) which uses an extra byte per 64-bit word. ECC modules usually carry a multiple of 9 instead of a multiple of 8 chips.

Ranking[edit]

Sometimes memory modules are designed with two or more independent sets of DRAM chips connected to the same address and data buses; each such set is called a rank. Ranks that share the same slot, only one rank may be accessed at any given time; it is specified by activating the corresponding rank's chip select (CS) signal. The other ranks on the module are deactivated for the duration of the operation by having their corresponding CS signals deactivated. DIMMs are currently being commonly manufactured with up to four ranks per module. Consumer DIMM vendors have recently begun to distinguish between single and dual ranked DIMMs.

After a memory word is fetched, the memory is typically inaccessible for an extended period of time while the sense amplifiers are charged for access of the next cell. By interleaving the memory (e.g. cells 0, 4, 8, etc. are stored together in one rank), sequential memory accesses can be performed more rapidly because sense amplifiers have 3 cycles of idle time for recharging, between accesses.

DIMMs are often referred to as 'single-sided' or 'double-sided' to describe whether the DRAM chips are located on one or both sides of the module's printed circuit board (PCB). However, these terms may cause confusion, as the physical layout of the chips does not necessarily relate to how they are logically organized or accessed.

JEDEC decided that the terms 'dual-sided', 'double-sided', or 'dual-banked' were not correct when applied to registered DIMMs (RDIMMs).

Organization[edit]

Most DIMMs are built using '×4' ('by four') or '×8' ('by eight') memory chips with nine chips per side; '×4' and '×8' refer to the data width of the DRAM chips in bits.

In the case of '×4' registered DIMMs, the data width per side is 36 bits; therefore, the memory controller (which requires 72 bits) needs to address both sides at the same time to read or write the data it needs. In this case, the two-sided module is single-ranked. For '×8' registered DIMMs, each side is 72 bits wide, so the memory controller only addresses one side at a time (the two-sided module is dual-ranked).

The above example applies to ECC memory that stores 72 bits instead of the more common 64. There would also be one extra chip per group of eight, which is not counted.

Speeds[edit]

For various technologies, there are certain bus and device clock frequencies that are standardized; there is also a decided nomenclature for each of these speeds for each type.

DIMMs based on Single Data Rate (SDR) DRAM have the same bus frequency for data, address and control lines. DIMMs based on Double Data Rate (DDR) DRAM have data but not the strobe at double the rate of the clock; this is achieved by clocking on both the rising and falling edge of the data strobes. Power consumption and voltage gradually became lower with each generation of DDR-based DIMMs.

Form factors[edit]

Several form factors are commonly used in DIMMs. Single Data Rate Synchronous DRAM (SDR SDRAM) DIMMs were primarily manufactured in 1.5 inches (38 mm) and 1.7 inches (43 mm) heights. When 1U rackmount servers started becoming popular, these form factor registered DIMMs had to plug into angled DIMM sockets to fit in the 1.75 inches (44 mm) high box. To alleviate this issue, the next standards of DDR DIMMs were created with a 'low profile' (LP) height of around 1.2 inches (30 mm). These fit into vertical DIMM sockets for a 1U platform.

With the advent of blade servers, angled slots have once again become common in order to accommodate LP form factor DIMMs in these space-constrained boxes. This led to the development of the Very Low Profile (VLP) form factor DIMM with a height of around 0.72 inches (18 mm). The DDR3 JEDEC standard for VLP DIMM height is around 0.740 inches (18.8 mm). These will fit vertically in ATCA systems.

Full-height 240-pin DDR2 and DDR3 DIMMs are all specified at a height of around 1.18 inches (30 mm) by standards set by JEDEC. These form factors include 240-pin DIMM, SODIMM, Mini-DIMM and Micro-DIMM.^[2]

Full-height 288-pin DDR4 DIMMs are slightly taller than their DDR3 counterparts at 1.23 inches (31 mm). Similarly, VLP DDR4 DIMMs are also marginally taller than their DDR3 equivalent at nearly 0.74 inches (19 mm).^[3]

As of Q2 2017, Asus has had a PCI-E based 'DIMM.2', which has a similar socket to DDR3 DIMMs and is used to put in a module to connect up to two M.2NVMe solid-state drives. However, it cannot use common DDR type ram and does not have much support other than Asus.^{[citation needed]}

See also[edit]

• Dual in-line package (DIP)
• Memory geometry – logical configuration of RAM modules (channels, ranks, banks, etc.)
• NVDIMM – non-volatile DIMM
• Rambus in-line memory module (RIMM)
• Single in-line memory module (SIMM)
• Single in-line package (SIP)
• Zig-zag in-line package (ZIP)

References[edit]

1. ^Temperature Sensor in DIMM memory modules
2. ^JEDEC MO-269J Whitepaper., accessed Aug. 20, 2014.
3. ^JEDEC MO-309E Whitepaper., accessed Aug. 20, 2014.

External links[edit]